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Lately, the chip giant Intel announced that its 10nm chip will begin shipping in the second half of 2019.
The development of Moore's law was ineffective today. In the past years, Intel has been developing smoothly in a 10 nanometer process, which is almost dystocia, so that since the release of the Skylake chip in 2015, the company scrubbed a 14 nanometer process and even rumors It is said that Intel completely abandoned the 10nm plan.
Luckily, Intel announced that it will next release the next generation Core and Xeon chips of the next generation of Sunny Cove.
It is understandable that Sunny Cove is an improved micro architecture, built on a 10-nanometer process, and Intel is not a 10-mm full-body chip. Instead, it uses Foveros technology for joint packaging of various versions and various parts. 10nm process technology.
Foveros is a logical chip 3D stacking technology that was previously used on memory chips, but it's still difficult to use on the CPU.from
Foveros technology combines complex logic chips to provide greater functionality and matching the components of the various processor parts with an appropriate manufacturing process.
For example, a high-performance processor core can be built on the highest-performance 10-nanometer process, but the integrated I / O connectivity of USB, Wi-Fi, Ethernet and PCIe does not require such high performance. It might make sense to use the 14nm process or even 22nm. Because its capacity is sufficient, energy consumption and costs are much lower.
Foveros means that the processor can integrate these components into different processes. These various components can be packed together in parallel with a higher density and a smaller surface of the chips.
When the chip is designed and developed at an early stage, it will take place with the lumber industry, then packaged and produced masses. At present, much-known chip foundries include companies such as Intel, Samsung, TSMC and Grofund.
Since 1995, semiconductor process technology has developed from 500nm, 350nm and 250nm to today's 28nm, 10nm and 7nm. At present, most foundries invest heavily in the 7nm production line and successfully produce the associated samples.
The so-called nano process is the width of the gateway of the transistor CMOSFET, which is the length of the gate. The length of the door can be divided into the length of the lithographic door and the actual length of the door. Due to the diffraction of light in lithography and in the steps of ion implantation, etching, plasma flushing, heat treatment, etc., the length of the lithographic doors and the actual length of the doors are inconsistent.
In addition, under the same process technology, the actual length of the door will be different. Intel's comparison with opponents on the 10nm process is enough to illustrate the problem.
The lower the length of the door, there are two major advantages: first, to increase the density of the transistor, several transistors can be manufactured on the same size silicone blade, the computational power will be stronger, the other advantage is to reduce energy consumption, because the length of the gate determines the current through the loss at that time if the narrower the width, the lower the energy consumption.
That's why many chip makers accept advanced process technologies, howeverfrom
If real demand, input costs and technology maturity are introduced into the system, many chip makers will not follow the latest process technology blindly, and will choose the most cost-effective process at a given time hub.
According to the Gartner consulting company,from
The total cost of the 10nm chip design is around $ 120 million and the 7nm chip is $ 271 million, which is twice as much as 10nm.from
So not all companies can catch the latest technology.
The process of manufacturing chips chosen by smart car companies is between 12 nm and 40 nm, and the strategy is relatively conservative and conservative.
The results of the research show that the improvement of the capacities and the reduction of costs caused by the development of the chip process technology has become a 28 nm process hub, and then we continue with a more advanced process, and the costs do not fall.from
From a commercial point of view, for some civilian scenarios, such as smart cars, 28 nm is the best cost-effective technology.
At the beginning of 2018, TSMC, the world's leading chip maker, announced that it would retain a 28-nanometer process line. As a long-term longevity technology, this generation of technology is the most stable and widely used. Although current technology has evolved to 7nm, even 5nm.
When a large factory and a startup company select chipboard at the same time, it will have an appropriate priority for the production of orders in the future. Fortunately, the technology of overlapping overlapping processes chosen by these companies is not so high.
The relevant companies indicated in the survey that they are like TSMC, but are still very strict in the industry. A number of qualifications, including the background of the company, technology and future products, must be applied for the implementation of chipstream and mass production in the TSMC. It is assumed that the other party will come to the company to conduct an investigation and ultimately determine whether to open an account for the company.
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